Title :
Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point accelerators
Author_Institution :
Institute of Information Theory and Automation, UTIA AV CR v.v.i., Prague, Czech Republic
fDate :
7/1/2015 12:00:00 AM
Abstract :
This paper briefly describes basic Kintex7 FPGA video pipe infrastructure for UTIA demonstrator in the ARTEMIS JU project ALMARVI. The video pipeline is combined with the run-time reprogrammable vector floating point EdkDSP accelerators on the same FPGA chip.
Keywords :
"Streaming media","Clocks","Finite impulse response filters","Least squares approximations","Computational modeling","Field programmable gate arrays","Microprogramming"
Conference_Titel :
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on
DOI :
10.1109/SAMOS.2015.7363690
