A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO), the DPLL achieves -110dBc/Hz and -130dBc/Hz for in-band and 1MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz. The digital PLL is simulated in a 65nm CMOS process, consuming 11.2mW from a 1.0V supply.