Secured-by-design FPGA: look-up tables and switch-boxes

A circuit technique based on hardware replication improves the robustness of the FPGA circuitry against dynamic and/or static power attacks. Due to its nMOS-MUX based structure, the proposed circuit also exhibits an increased robustness against early evaluation attacks and those based on glitches. The secured LUT and switch are 3.4× and 1.5× larger than their standard counterparts, respectively. Given the achieved robustness against both dynamic and static power attacks, while FPGA configurability is preserved, this is a good trade-off.