• DocumentCode
    3718240
  • Title

    evercodeML: A formal language for SoC integration

  • Author

    Jos? I. Villar;Jorge Juan;David Guerrero;Manuel J. Bellido;Juli?n Viejo

  • Author_Institution
    Departamento de Tecnolog?a Electr?nica, Universidad de Sevilla, Spain
  • fYear
    2015
  • fDate
    6/1/2015 12:00:00 AM
  • Firstpage
    23
  • Lastpage
    26
  • Abstract
    Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex systems with very heterogeneous IP-cores and module providers. This contribution introduces a formal language for SoC integration that overcomes these limitations.
  • Keywords
    "Hardware design languages","Generators","System integration","Field programmable gate arrays","Hardware","Packaging","XML"
  • Publisher
    ieee
  • Conference_Titel
    Electronic System Level Synthesis Conference (ESLsyn), 2015
  • ISSN
    2117-4628
  • Type

    conf

  • Filename
    7365121
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3718240