Analysis of interconnection reliability of dielectric layer for wafer level chip scale package

This study investigates of the mechanical properties of wafer level chip scale package (WLCSP) without under bump metallurgy (UBM) layer which is defined as 3-mask WLCSP package. The mechanical properties of dielectric layer, such as Young´s modulus and hardness, were measured by nanoindentation systems. Simple models were developed to simulate the thermal stress and predict the failure area. In this study, the dielectric layer crack phenomena were examined. The nonlinear mechanical properties of dielectric layer measured by nanoindentation were used as the simulation parameters, based on which the thermal stress by simulation was obtained.