A novel flow to optimize package power distribution network design

Power Integrity (PI) is an important topic in today´s high-speed interface designs, and the power distribution network (PDN) is a major factor in the package design. This research we propose an effective design method for a multi-layer and complex package design. The first section of this paper is to perform the current density to fast find the bottleneck of draft design for the DDR core power and DDR IO power planes. Due to the poor ball assignment, the longer current path is detected from the current density map, and then to adjust the ball assignment to change the current density. The second section of the paper is modeling the package, including resistance, inductance parasitic and PDN impedance extractions based on the S-parameter simulation. From optimizing the package design and the chip-package co-simulation to analyze the SSN and dynamic power noise are estimated in Section III. Finally, conclusions are given.