• DocumentCode
    3718369
  • Title

    Enabling wet etch process for TSV reveal high-volume manufacturing

  • Author

    Laura Mauer;John Taddei;John Clark;Erwan Le Roy

  • Author_Institution
    Veeco Precision Surface Processing LLC, 185 Gibraltar Road, Horsham, PA 19044 USA
  • fYear
    2015
  • Firstpage
    101
  • Lastpage
    103
  • Abstract
    2.5D and 3D packaging continues to be a popular topic within the semiconductor industry. Several announcements have shown signs of adoption for the new packaging technology, especially for stacked DRAMi. The reveal of the Through Silicon Via (TSV) is a critical step within this packaging integration sequence. However, the biggest challenge delaying high-volume manufacturing is the cost. This article presents a two-step wet etch technique as an economical process for achieving uniformly revealed vias.
  • Keywords
    "Silicon","Rough surfaces","Surface roughness","Etching","Three-dimensional displays","Through-silicon vias"
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2015 10th International
  • Print_ISBN
    978-1-4673-9690-5
  • Type

    conf

  • DOI
    10.1109/IMPACT.2015.7365257
  • Filename
    7365257
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3718369