Enabling wet etch process for TSV reveal high-volume manufacturing

2.5D and 3D packaging continues to be a popular topic within the semiconductor industry. Several announcements have shown signs of adoption for the new packaging technology, especially for stacked DRAMi. The reveal of the Through Silicon Via (TSV) is a critical step within this packaging integration sequence. However, the biggest challenge delaying high-volume manufacturing is the cost. This article presents a two-step wet etch technique as an economical process for achieving uniformly revealed vias.