Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both SEU and SET with reduced power consumption. The approach utilizes commercial CAD tools. An advanced encryption system is implemented with the proposed design is compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation by 18% over an improved version of the prior approach, with negligible area impact.