DAO: Dual module redundancy with AND/OR logic voter for FPGA hardening

As device size shrinks, SRAM-based FPGAs are increasingly prone to be affected by single-event upsets (SEUs). SEU mitigation techniques for FPGAs are mostly expensive in terms of area and power costs. This paper proposes a new design for FPGA hardening using dual-modular redundancy (DMR). The duplication operates on lookup-table (LUT) level, and each pair of identical LUTs will be voted by an AND or OR logic voter. By virtue of the fault-masking effect of AND/OR logic, certain faults in duplicated LUTs will not propagate to the next level of the hardened circuit. Results on MCNC´91 benchmarks show that the proposed method can reduce 90% faults with an area overhead of 100% additional number of LUTs, and the runtime of the proposed algorithm is much shorter than other existing methods.