Communication scheduling and buslet synthesis for low-interconnect HLS designs

Current nanoscale designs are highly interconnect dominated, taking about 70% of the chip area. Interconnects also consume significant dynamic power, and about 60% of signal delays. It is thus important to be able to synthesize much lower interconnect-complexity designs than are possible with current high-level synthesis (HLS) tools and algorithms. Towards that end, we have developed the new paradigms of: a) flexibly-structured buslets that connect a few “neighborhood” functional units (FUs) instead of dedicated interconnect between pairs of FUs, thereby sharing interconnects among a number of FU pairs that need to communicate; b) communication scheduling (followed by standard operation scheduling) in which communication between FUs are scheduled at appropriate times to minimize the number of buslets needed, subject to buslet cardinality constraints (for the purpose of upper bounding signal delay). Using a force-directed technique for communication and operation scheduling, and a chronological algorithm that simultaneously performs communication-to-buslet, FU-connections-to-buslets and operation-to-FU binding, we obtain significant wirelength (WL) reduction in the range of 35-71% in our designs compared to conventional FDS-based designs with dedicated-interconnects between communicating FU pairs.