• DocumentCode
    3723431
  • Title

    TAU 2015 contest on incremental timing analysis

  • Author

    Jin Hu;Greg Schaeffer;Vibhor Garg

  • Author_Institution
    IBM Systems and Technology Group, Hopewell Junction, NY, USA
  • fYear
    2015
  • Firstpage
    882
  • Lastpage
    889
  • Abstract
    Among timing analysis applications, timing-driven operations are imperative for the success of optimization flows, such as placement, routing, logic synthesis, and physical synthesis. Optimization transforms change the design, and therefore have the potential to significantly affect timing information. As such, timing must be kept current to ensure slack integrity and timing closure. For reasonable turnaround and performance, the timer should incrementally update the affected portion of the design. The aim of the TAU 2015 timing contest is to seek novel ideas for incremental timing analysis by: (i) introducing the concept and motivating the importance of incremental timing analysis, (ii) encourage novel parallelization techniques (including multi-threading), and (iii) facilitating the creation of an incremental timing analysis framework with benchmarks to further advance this research area.
  • Keywords
    "Clocks","Delays","Integrated circuit interconnections","Integrated circuit modeling","Optimization","Logic gates"
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design (ICCAD), 2015 IEEE/ACM International Conference on
  • Type

    conf

  • DOI
    10.1109/ICCAD.2015.7372664
  • Filename
    7372664