DocumentCode :
3723432
Title :
iTimerC 2.0: Fast incremental timing and CPPR analysis
Author :
Pei-Yu Lee;Iris Hui-Ru Jiang;Cheng-Ruei Li;Wei-Lun Chiu;Yu-Ming Yang
Author_Institution :
Dept. of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan
fYear :
2015
Firstpage :
890
Lastpage :
894
Abstract :
To achieve timing closure, performance-driven optimizations are repeatedly performed throughout the modern IC design flow. Along with these optimization operations, how to incrementally update timing information efficiently and accurately becomes a crucial task for fast turnaround time. On the other hand, to avoid wasteful over-optimization, clock path pessimism should be removed during timing analysis. In order to provide prompt timing information without over-pessimism during iterative optimizations, in this paper, we aim at fast incremental timing and CPPR analysis. We present two delicate techniques, lazy evaluation and lazy propagation, to avoid redundant updates. Our experiments are conducted on the benchmark suite released by TAU 2015 timing analysis contest. Experimental results show that our timer delivers the best results in terms of accuracy, runtime, and memory over all participating teams.
Keywords :
"Clocks","Logic gates","Optimization","Libraries","Delays","Pins"
Publisher :
ieee
Conference_Titel :
Computer-Aided Design (ICCAD), 2015 IEEE/ACM International Conference on
Type :
conf
DOI :
10.1109/ICCAD.2015.7372665
Filename :
7372665
Link To Document :
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