Title :
An efficient diminished-1 modulo 2n + 1 multiplier using signed-digit number representation
Author :
Yuuki Tanaka;Shugang Wei
Author_Institution :
Division of Mechanical Science and Technology, Faculty of Science and Technology, Gunma University, 373-0057, Japan
Abstract :
In this paper, we propose a new modulo 2n + 1 multiplier for the diminished-1 representation. Our algorithm generates [n/4] +1 Signed-Digit(SD) numbers of n digits as the partial products and sums up these numbers by a multi-operand modulo 2n +1 SD adder. We found that the proposed multiplier is smaller and faster than several proposed circuits.
Keywords :
"Yttrium","Adders","Logic gates","Logic circuits","Electronic mail","Very large scale integration","Wires"
Conference_Titel :
TENCON 2015 - 2015 IEEE Region 10 Conference
Print_ISBN :
978-1-4799-8639-2
Electronic_ISBN :
2159-3450
DOI :
10.1109/TENCON.2015.7372727
