Non-volatile D-latch for sequential logic circuits using memristors

This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL is more energy efficient than the CMOS based volatile D-latch. The energy required by NVDL to store or retrieve the data is 1.5 times lesser than the CMOS based D-latch. In addition, the NVDL switching speed is increased by 1.54 times when compared with previous NV latches design.