Drain side super junctions co-worked with “npn” arranged SCRs on ESD robustness in the 45-V nLDMOS devices

For the anti-ESD reliability consideration, the drain-side with super-junction structures and “npn” embedded type SCRs of nLDMOS transistors are investigated in this paper. From the experimental data, we can find that the layout manner of super-junction types in the drain-side have positive impacts on the anti-ESD capability. On the other hand, as the drain-side added another item i.e. an embedded “npn”-type SCR structure, in which this new composite device has bad influences on reliabilities than that of the corresponding nLDMOS-SJ DUT. In other words, the layout type of super-junction nLDMOS has a higher It2 values; the anti-ESD improvement is more than 18.2% as compared with the reference DUT. However, it can be summarized that this drain-side “npn” stripe-type SCR of nLDMOS device is not a good choice for the anti-ESD robustness improvement.