Design and implementation of a variable step-size transform domain NLMS adaptive filter

This paper presents a new structure for the variable step-size transform domain NLMS (VSS-TDNLMS) adaptive filter. The pipelining of VSS-TDNLMS is achieved by introducing an amount of delay into the feedback loops. The transform function is realized efficiently by classical recursive implementation. To reduce the hardware complexity, we use multiplier-less implementation to realize the constant coefficient multiplication. The structure is successfully implemented in FPGA, and the results show that it improves the convergence speed by almost 18 times and 1.5 times over the D-LMS and D-TDNLMS structures, respectively.