Improved miller capacitance of new heterostructure silicon-on-insulator tunnel FET

This work presents the comparative study of three different heterojunction SOI-TFET architectures: conventional SOI-TFET, gate overlapped on source SOI-TFET and oxide overlapped on source SOI-TFET. Gate oxide overlapped on source SOI-TFET reported significant improvement in ON current (18μ A/μm) and Ion/Ioff ratio (1010). In addition to significantly low average subthreshold swing (22 mV / dec), the Miller capacitance is also improved as compared to conventional heterojunction SOI-TFET. The proposed device is optimized using 2D Synopsys TCAD simulation and it reveal that the simple oxide overlap on the germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance.