Chip-package-PCB co-simulation for power integrity design at the early design stage

We investigated a chip-package-PCB co-simulation method for power integrity design at the early design stage. Due to the number of design parameters that need to be surveyed to optimize power integrity at this stage, the method requires fast power integrity analysis and a convenient way to revise design parameters. By applying a PEEC method with different mesh sizes for each component and reducing the input cost for the power and ground plane layout, we can reduce simulation costs with permissible levels of simulation error.