3D device simulation of 6T SRAM cell with voltage scaling in 90nm CMOS

In VLSI system the design of memory is very crucial if we look from area, power and performance perspective. According to the report of ITRS it is expected that memories will occupy up to 95% of the chip area in 2015. SRAM cell provides the highest challenge to device designers as it requires high integration. It is the most reliable memory and is widely used for critical operations in the chip design but at the same time it occupies a considerable space in the layout. SRAM, a 3D device exhibits altogether different characteristics when compared with discrete NMOS and PMOS transistors due to stress and proximity effects etc. In this research paper, we will simulate 6T SRAM cell as a single continuous 3-D structure rather than a set of 6 individual transistors and then predict its electrical behaviour using TCAD simulation tool. Using this 3-D model, impact of voltage scaling on the performance of SRAM is analyzed.