A new energy efficient two phase adiabatic logic for low power VLSI applications

This paper proposes a 4:1 Multiplexer circuit based on a new energy efficient two phase clocked adiabatic logic. Inverter based on the proposed technique has been compared with CMOS and PFAL (positive feedback adiabatic logic) based inverters. Results show significant power saving in the 10 to 200MHz range. The proposed multiplexer circuit dissipates 0.35μW power at a frequency of 10MHz and a load capacitance of 1fF. To verify the proposed circuit, TSPICE simulations were carried out using 90nm technology.