Effect of process, voltage and temperature (PVT) variations In LECTOR-B (leakage reduction technique) at 70 nm technology node

For high performance and higher computational capability in VLSI circuits feature size should be small. As continue scaling down the dimension of transistors in very deep sub-micron regime parameter variation becomes a critical issue. The performance of any logic circuit decreases by variability of parameters hence increasing leakage current. To overcome the variability issue in sub-micron regime the design must be aware of variations. In this paper LECTOR-B (A leakage reduction technique) is used to analyze the variability issue. This technique reduces leakage current as well as it mitigates the variability issue with small delay penalty. Various process, voltage and temperature (PVT) variations are analyzed at 70 nm technology node for an inverter using tanner EDA tool. Simulation result shows that LECTOR-B technique has less affect of PVT variations as compare to conventional circuit.