Hardware optimization of complex multiplication scheme for DSP application

Complex multiplications are the backbones of almost all Digital Signal Processing (DSP) algorithms and several other scientific applications. Complexity Reduction of these operations at architectural level or algorithmic level can certainly save the chip area, which ultimately can be a driver parameter for selection of power or speed optimized architectures. Improvement in these performance parameters opens up the new opportunities for the technological developments. This work is based on the computational complexity reduction of complex multiplier scheme. The conventional complex multiplier scheme is optimized in terms of area and power and a comparative with respect to the conventional scheme is presented.