A stable and power efficient SRAM cell

In this paper, we designed a 9T SRAM cell using dual voltage threshold (DVT) and stacking effect. To achieve high density, low power and high performance, device scaling has been continuously done that result in increase in leakage power dissipation. At sub-micron technology, about 30% of total power dissipation is due to leakage power dissipation. The purpose of this paper is to analyze the Performance parameters like SNM (static noise margin) in all modes of operations, leakage power dissipation, writes and read access delay. In this paper, we analyzed the comparative parameters in 6T, 7T and proposed 9T SRAM Cell. The proposed 9T SRAM Cell gives improved SNM and reduced leakage power at the cost of small area overhead. The circuit was implemented using cadence Virtuoso tools in 180-nm technology.