A low power 16 bit BCD adder using different power reduction techniqes

In this paper, we designed a 16-bit BCD adder using power gating design, dual threshold voltage (DVT) and LECTOR technique. To achieve high density, low power and high performance device scaling has been continuously done that results in increase in leakage power dissipation. At nanometers technology, about 30% of total power dissipation is due to leakage power dissipation. The purpose of this paper to analyze the static power reduction techniques which are mentioned above. In this paper, performance parameters like Average power dissipation and delay are compared in each of these four techniques. It uses 1-bit full adder using CMOS logic. The circuit was implemented using cadence Virtuoso tools in 180-nm technology.