A novel pipeline topology with 4:1 MUX-Latches for serial link

In the research of low power VLSI circuits, the use and implementation of Transmission Gate Based MUX-Latches for serial link interfaces has gained more attention at the gate level design. Multiplexer-latches (MUX-Latches) possess the logic function of combinational circuits and storing capacity of sequential circuits. By using pipeline topology with Transmission Gate MUX-Latch, many latch gates for sequencing and clock load can be removed. 4:1 MUX-Latches using transmission gate in pipeline topology to reduce gate count is proposed in this paper. The proposed design dissipates less power and provides high switching speed for serial link interfacing. The 4:1 MUX-Latch using Transmission Gate design implemented in 32nm technology consumes 2.353μW power for 8.33 Gb/s data rate. This proposed work is better than conventional MUX-FFs as MUX-Latch is a level sensitive device and provides faster switching speed than flip-flops in serial link interfacing.