Ultra low power multiplexer design using variation in CMOS inverter

Low power VLSI demands for the development of promptly design methodologies to reduce the power consumption or power dissipation up to a level. To meet the growing demand, we propose a new low power multiplexer cell by reducing the MOS Transistor count that reduces the serious threshold loss problem. In the proposed circuit we use CMOS technique for designing of ultra low power multiplexer because in CMOS techniques there is almost zero static power dissipation. In conventional multiplexer there are 12 number of transistors which consumes more power as compare to proposed multiplexer which include only 8 number of transistor in CMOS form, considerably increases the speed and decreases the power when compared to the conventional multiplexer. Also proposed circuit consumes less power as compare to dynamic multiplexer.