An architecture based routing for heterogeneous fat tree network on chip

With the evolution of network on chip, a number of topologies depicting the structure of the network came up. Classical network designs like star, mesh, ring were initially used but ongoing to its wide range of applications in real life network on a chip was much applicable in real time so factors like area, latency, placements of IPs were to be addressed. As a result, many new topologies like torus, spin, butterfly evolved which could address these issues. One of such topology which has been widely used is the fat tree. Unlike the conventional tree used in computation, the fat tree was more like a real tree making it highly efficient for supercomputing. Although, the architecture and routing in this network is predesigned, but it has been implemented in different environments and with different techniques. Here, we have designed an architecture based routing for the fat tree network with heterogeneous switches. Based on the results presented, it is seen that the new approach is performing much efficiently.