High efficient carrier phase synchronization for SDR using CORDIC implemented on an FPGA

This paper is devoted to the proposal of a highly efficient carrier phase synchronization subsystem for Software Defined Receiver. The proposed feedback phase-locked loop carrier synchronizer is suitable for parallel implementation on an FPGA for QPSK with the possibility of extension for m-QAM modulation. Direct Digital Synthesizer uses CORDIC algorithm in rotation mode for calculation of the sine and cosine of an angle. The angle of rotation is the uncompensated carrier phase offset. The carrier phase offset is derived by the closed-loop path created by phase error detector, PLL loop filter and accumulator control block. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented.