Title :
Reconfigurable ALU optimization
Author :
Prashan B. Weerasinghe;Chathura De. Silva;Sanath Jayasena
Author_Institution :
Computer Science & Engineering Department, University of Moratuwa, Sri Lanka
Abstract :
The RALU optimisation research targeted to develop a soft processor, which is capable of a dynamic optimization of resource utilisation and increased processor throughput by changing its structure according to the running instruction. The RALU shows higher instruction gain and clock cycle gain compared to 8 bit microprocessor in similar scale. So the RALU approach provides solution to higher resource critical FPGA based design by improving the resource utilisation and providing higher processor throughput.
Keywords :
"Field programmable gate arrays","Microcontrollers"
Conference_Titel :
Advances in ICT for Emerging Regions (ICTer), 2015 Fifteenth International Conference on
Print_ISBN :
978-1-4673-9440-6
DOI :
10.1109/ICTER.2015.7377702