A 0.55V 100MHz ADPLL with ?? LDO and Relaxation DCO in 65nm CMOS

A 0.55V 100MHz LDO-embedded ADPLL is implemented in 65nm CMOS. A digitally-controlled relaxation oscillator (DCRXO) with a variable-threshold inverter and a digital calibration circuit is designed for robust start up under ultra-low supply voltage. A ΔΣ modulated pseudo-digital LDO provides a PVT-insensitive dithered internal voltage for the DCRXO. The 100MHz ADPLL including the LDO consumes a 67μW from a 0.55V supply and achieves the phase noise of -82.9dBc/Hz at 1MHz offset frequency. The LDO achieves >20dB PSRR when sinusoidal noise is injected to the supply.