An approach to reducing the time complexity of analog active circuit evolutionary design

Analog active circuits are of great important in integrated circuits design. It has practical values to apply the automatic analog active circuit evolutionary design in engineering application. While the key problem of applying the evolutionary design in engineering application is the large time complexity (namely, the large time complexity means lots of time-consuming). We propose a method of controlling the simulating accuracy in the circuit evolution to reduce the time complexity. The approach can be used to control the scale of simulating data by controlling the simulating accuracy. At the same time, the time-consuming of simulation is controlled. Through the experiment of active low-pass circuit design, the approach is verified significant effect especially in automatic analog active circuit evolutionary design on industrial platform.