Five staged pipelined processor with self clocking mechanism

With the advent of synchronous systems we have come across various difficulties and problems associated with them, mainly like clock skew, power consumption, etc. The idea of making systems clockless has been proposed numerous times and has been explored in great detail. Although we see that even those systems are not free from their own disadvantages like false triggering, handshaking hardware requirement, etc. Since both systems, synchronous and asynchronous show their own set of advantages and disadvantages the logical step is to find a mix of each of them in an overall system. This paper proposes an idea of a five stage pipelined processor with both synchronous and asynchronous blocks combined together to take the best of both ideologies. We intend to mix both these systems together by making use of the handshake signals from the asynchronous systems to generate a clock for the synchronous systems. This makes the processor give output with an average time delay lesser than the worst case delay of the synchronous processor, yet keeping the benefits from the synchronous system intact and adding various other benefits also.