The impact of knowing the impedance of the lines used in the TRL calibration on the load-pull characterization of power transistors

In this paper, the impact of knowing the impedance of the lines used in the TRL calibration (Z) on the load-pull (LP) characterization of power transistors is assessed. Relevant parameters, such as input impedance (Z_in), load impedance (Z_ld) and large-signal gain are considered. By using the ABCD-parameters matrix formalism in the calibration of the LP measurement setup, closed form expressions for evaluating the impact of knowing Z on the calculation of these parameters are presented. It is demonstrated that knowing Z is of paramount importance in the calculation of Z_in and Z_ld. Regarding the gain, it is demonstrated that while the voltage and current gains do not depend on the knowledge of Z, the gain expressed as the ratio of the transmitted to incident waves does.