A low-power task mapping method for network on chip

When more and more processor cores are integrated onto a single chip, the computing ability has been improved dramatically. And the power consumed by the cores is also increased. More tasks can run in parallel for higher performance. It is a new challenge on how to map the tasks to the cores. The suitable task mapping method can enhance the parallelism of the system. However, it is still a problem to reduce the power-consumption. In this paper, a novel method is proposed to map the tasks to the cores efficiently with lower power consumption. The case study and related experimental results show that our method can have better performance and reduced power consumption.