DocumentCode :
3731252
Title :
The FPGA design of JPEG-LS image lossless decompression IP core
Author :
Lihua Deng;Zhenghua Huang
Author_Institution :
Institute for Pattern Recognition and Artificial, Intelligence Huazhong University of Science and Technology, Wuhan, China
fYear :
2015
Firstpage :
2199
Lastpage :
2203
Abstract :
This paper presents the key optimization techniques for an efficient accelerator implementation in an image decoder IP core design for real-time Joint Photographic Experts Group Lossless (JPEG-LS) decoding. Pipeline architecture, frequency multiplication technique and accelerator elements have been utilized to enhance the throughput capability. Improved parameters mapping schemes have been adopted for the purpose of low complexity and small chip die area. It has been proved that these hardware-oriented optimization techniques make the decoder meet the requirements of the IP core implementation. The proposed optimization techniques have been verified in the implementation of the JPEG-LS decoder IP, and then validated in a real satellite image receiving system.
Keywords :
"Computational modeling","Context modeling","Context","Optimization","Predictive models","Image reconstruction","Random access memory"
Publisher :
ieee
Conference_Titel :
Chinese Automation Congress (CAC), 2015
Type :
conf
DOI :
10.1109/CAC.2015.7382869
Filename :
7382869
Link To Document :
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