The FPGA design of JPEG-LS image lossless decompression IP core

This paper presents the key optimization techniques for an efficient accelerator implementation in an image decoder IP core design for real-time Joint Photographic Experts Group Lossless (JPEG-LS) decoding. Pipeline architecture, frequency multiplication technique and accelerator elements have been utilized to enhance the throughput capability. Improved parameters mapping schemes have been adopted for the purpose of low complexity and small chip die area. It has been proved that these hardware-oriented optimization techniques make the decoder meet the requirements of the IP core implementation. The proposed optimization techniques have been verified in the implementation of the JPEG-LS decoder IP, and then validated in a real satellite image receiving system.