DocumentCode :
3731544
Title :
Vortex Transitional Memory Developed with Nb 4-Layer, 10-kA/cm² Fabrication Process
Author :
Yuto Komura;Masamitsu Tanaka;Shuichi Nagasawa;Ali Bozbey;Akira Fujimaki
Author_Institution :
Nagoya Univ., Nagoya, Japan
fYear :
2015
fDate :
7/1/2015 12:00:00 AM
Firstpage :
1
Lastpage :
3
Abstract :
We report random access memories (RAMs) based on vortex transitional (VT) memory cell developed with the newly developed AIST 10-kA/cm2, Nb 4-layer fabrication process, called High-Speed Standard Process (HSTP). We obtained more effective mutual coupling structure by fully use of all the wiring layer, and successfully reduced the cell size to 25 μm square, which indicated roughly 50% increase in density compared to the previous design. We reduced the critical currents of Josephson junctions and load resistance to be matched with driving circuitry. We tested the miniaturized VT memory cell, and obtained a sufficient margin width of ~15%, and also confirmed correct operations of the other components, including a latching driver and address decoder.
Keywords :
"Random access memory","Current measurement","Yttrium","Niobium","Transmission line measurements","Fabrication","Critical current density (superconductivity)"
Publisher :
ieee
Conference_Titel :
Superconductive Electronics Conference (ISEC), 2015 15th International
Type :
conf
DOI :
10.1109/ISEC.2015.7383489
Filename :
7383489
Link To Document :
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