A Time-Predictable Model of Computation

Effectiveness of timing analysis of real-time applications depends on the timing predictability of the underlying execution platform. Modern hardware architectures improve average case performance using complex features. However, these features make Worst Case Execution Time (WCET) analysis complicated often leading to pessimistic derived worst case execution time. We present the preliminary design of Synchronous Control Asynchronous Dataflow (SCAD) - a new model of computation targeting time-predictability and competitive performance. Inorder execution of instructions and capability to bypass memory accesses imparts timing predictability to SCAD computational model. We also motivate a code generation technique to optimally utilize the memory bypassing capability of SCAD and that results in increased instruction level parallelism.