LTCC package for high-bandwidth logic to memory interconnection

Advancements in packaging technologies are required to meet the future bandwidth, and space- and energy-efficient demands of ICT systems. One of the key technologies is 2.5D packaging using a silicon interposer with through silicon vias (TSVs). However, forming the TSV and thinning the wafer makes the Si interposer´s cost high. Furthermore, using an organic substrate causes high electrical losses and warpage. We propose a low-temperature co-fired ceramics (LTCC) package with fine line layers to help alleviate these problems. The surface of the LTCC substrate is made very flat, so fine patterns with line/space that is 2/2μm can be formed. The LTCC package has been expected to decrease the necessary costs by simplifying the assembly process and introducing a panel-based process. Moreover, the LTCC substrate is more reliable than a Si interposer with an organic substrate and can transmit a high data rate signal at a lower loss. We demonstrated the possibility of high Bandwidth Memory (HBM) routing using the LTCC package.