DocumentCode :
3731731
Title :
Reduction of P/G impedance by edge plating
Author :
Seunghoon Yeon;Dong Gun Kam
Author_Institution :
Electrical Interconnect and Packaging Lab., Ajou University, Suwon, Korea
fYear :
2015
Firstpage :
221
Lastpage :
224
Abstract :
We propose a package tiling method for reducing the impedance of a power distribution network (PDN). The PDNs of two packages are directly connected by edge plating, rather than being connected through a board. Experimental results show that the proposed idea greatly reduces the loop impedance.
Keywords :
"Arrays","Plating","Impedance","Antenna arrays","Vehicles","Packaging"
Publisher :
ieee
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2015 IEEE
Type :
conf
DOI :
10.1109/EDAPS.2015.7383715
Filename :
7383715
Link To Document :
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