SIMAAH: RTL simulation accelerator for complex SoC´s

The EDA industry has recently witnessed the growing popularity of densely populated, IP rich SoC designs targeting high performance computing platforms. Such SoCs require effective logic simulation, with high levels of accuracy and throughput, for a fault free design and faster time to market. Hardware-Assisted Simulation (HAS) is the appropriate choice, while simulating such designs. Existing HAS suffer from performance bottlenecks introduced by the need to synthesize every new and revised RTL source codes onto target technology library. In this paper, we present SIMAAH (SIMulation Acceleration on an Array of Hypercell), a hardware-assisted RTL simulation accelerator, built on an interconnect of HyperCells [1][2]. A HyperCell is an array of highly parallel hardware structural units, comprising of ALUs, Custom Functional Units (CFU), and memory units. The Control Data Flow Graphs of the RTL source code of an SoC is adequately partitioned and scheduled on the HC array for an execution driven simulation. We achieve simulation acceleration on SIMAAH, at RTL abstraction, at improved speeds, and reduced synthesis overheads. SIMAAH, while trying to simulate standard application benchmarks, proves to be atleast 50 times faster than the existing industry standard event driven simulators like Modelsim.