DocumentCode
3731877
Title
Layered T full adder using Quantum-dot Cellular Automata
Author
Chiradeep Mukherjee;Aninda Sankar Sukla;Swarnendu Sekhar Basu;Ratna Chakrabarty;Angshuman Khan;Debashis De
Author_Institution
Department of Electronics & Communication Engineering, University of Engineering & Management, Jaipur, India
fYear
2015
fDate
7/1/2015 12:00:00 AM
Firstpage
1
Lastpage
6
Abstract
Fast changing world has driven technology towards a milestone where emerging technology like quantum-dot cellular automata (QCA) excels in terms of ultra-high packing density and extremely low power consumption. Quantum Cellular Automata has several deduction methodologies like Majority Voter, Universal QCA logic, FNZ logic & And-Or-Invert (AOI) logic none of which explores universal NAND-NOR based design in Boolean reduction techniques. This work proposes Layered T full adder with its basic primitive which works on the basis of universal NAND and NOR logic. Layered T gate is verified taking Coulomb´s law as the physics behind it. Layered T Gate is also used to implement full adder as primitive in processor based design which gives the best result in terms of cell requirement and area compared to the latest design.
Keywords
"Logic gates","Electric potential","Adders","Clocks","Inverters","Computer architecture","Microprocessors"
Publisher
ieee
Conference_Titel
Electronics, Computing and Communication Technologies (CONECCT), 2015 IEEE International Conference on
Type
conf
DOI
10.1109/CONECCT.2015.7383867
Filename
7383867
Link To Document