High performance SHA-2 core using the Round Pipelined Technique

Secured Hashing Algorithms are used to ensure the integrity and authenticity of data and data origin in order to achieve higher level of security. A proposed design for SHA-2 hashing functions (SHA-224, SHA-256, SHA-384, SHA-512) are implemented with fully iterative and pipelined architecture using Verilog HDL. For every hashing operation, throughput per slice plays a major role in optimized hardware design. In order to improve throughput per slice, the proposed design uses a Round Pipelined Technique (RPT) in hash functions. The SHA-2 algorithm outputs a message digest / hash of size 224, 256, 384 and 512-bits. Proposed research investigates optimization techniques in terms of area and frequency for SHA-2 hash functions on the FPGA and achieves higher throughput per slice. The proposed architecture is implemented on Xilinx Virtex-6 xc6vlx550t-2ff1759 FPGA device. Further, the fully iterative and Round Pipelined Technique based architectures are compared in terms of frequency and throughput per slice with other known published results. The proposed design for SHA-256 and SHA-512 with Round Pipelined Technique exhibits throughput per slice improvement of 57% and 17% respectively than other implementations.