A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS

This paper presented a frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS process. The FMCW signal is generated by a fractional-N PLL. The frequency doubling scheme can lower down the frequency of the PLL, reduce the required phase shifting range of phase shifter and the design complexity of the LO distributed network. The FMCW chirp bandwidth is 1.93 GHz from 76.92 to 78.85 GHz, while the root-mean-square frequency error is 674 kHz. The transmitting power is 12.9~13.2 dBm. The receive conversion gain is programmable from 47.8 dB to 100.7 dB. The two-path receiver noise figure is 10 dB and 6.6 dB at 400 kHz and 3.3 MHz IF frequencies, respectively. The transceiver consumes 343 mW power.