• DocumentCode
    3733919
  • Title

    A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC

  • Author

    Injoon Hong;Seongwook Park;Junyoung Park;Hoi-Jun Yoo

  • Author_Institution
    Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    An energy-efficient Deep Neural Network (DNN) processor is proposed for high-speed Visual Attention (VA) engine in a mobile vision SoC. The proposed embedded DNN realizes VA to rapidly find ROI tiles of potential target objects reducing ~70% of recognition workloads of vision processor. Compared to previous VA, the DNN VA reduces execution time by 90%, which results in 73.4% overall OR time reduction. Highly-parallel 200-way PEs are implemented in the DNN processor with 2D image sliding architecture, and only 3ms of DNN VA latency can be obtained. Also, the dual-mode PE configuration is proposed for both DNN and multi-layer-perceptron (MLP) to share same hardware for high energy efficiency. As a result, the proposed work achieves only 1.9nJ/pixel energy efficiency which is 7.7x smaller than state-of-the-art VA accelerator.
  • Keywords
    "Arrays","Hardware","Convolution","Visualization","Energy efficiency","Mobile communication"
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian
  • Type

    conf

  • DOI
    10.1109/ASSCC.2015.7387453
  • Filename
    7387453