A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer

A hybrid 2b-1b/cycle, two-step asynchronous SAR ADC exploiting the passive residue transfer technique is reported in this paper. The removal of the residue amplifier results in much savings in the time and power consumed for the residue transfer process. Moreover, the 2b-1b/cycle conversion scheme assisted by the asynchronous time allocation during the bit cycles further enhances the conversion speed. Fabricated in a 65-nm CMOS process, the prototype ADC measured an SNDR of 43.7 dB and an SFDR of 58.1 dB for a near Nyquist input. The total power consumption of the ADC is 5.0 mW and the achieved FoM is 35 fJ/conversion-step, all measured at a sample rate of 1.2 GS/s.