A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology

A 10-b pipeline ADC employing a coarse and a fine stage in the 4.5-b front-end is proposed to achieve low power in a 90-nm CMOS technology. The proposed stage highly relaxes the linearity requirement of the op amp and the complexity of the comparators. Hence, only a very low-gain amplifier is needed for interstage residue amplification without increasing the complexity of the comparator design. Operating at a 400-MS/s sampling rate, the ADC consumes 8.7 mW from a 1-V power supply. It achieves a signal-to-noise-plus-distortion (SNDR) better than 55 dB over the entire Nyquist band.