A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS

This paper reports a power-efficient equalizing receiver designed for multi-data rate serial link applications. It includes a continuous-time linear equalizer (CTLE) and a half-rate 1-tap speculative decision feedback equalizer (DFE). The proposed StrongArm latch-based DFE adopts a novel non-50% duty-cycle clocking scheme to achieve 20% higher speed compared with the conventional 50% duty-cycle clocking scheme solution. Implemented in a 65nm CMOS process with only regular threshold voltage transistors, the prototype receiver can operate up to 21Gb/s over a 25dB loss channel. At 21Gb/s, it consumes 20.08mW (0.96pJ/bit) power from a 1V supply.