A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors

A 576-bit LDPC decoder is designed using a charge-recovery logic family and in-package inductors. The decoder testchip is fabricated in a 65nm CMOS flip-chip process. Unlike all previously published high-performance charge-recovery chips, which use on-chip inductors to recover charge from parasitic capacitance, this charge-recovery design uses in-package inductors, avoiding the area overheads of on-chip inductors and achieving higher quality factors. Specifically, charge recovery is performed using 16 high-quality inductors that have been embedded in a custom-designed 6-layer FC-BGA package, significantly improving the area efficiency and energy consumption of the design compared to alternative implementations with on-chip inductors. When operating at 934MHz, the decoder consumes 3.2pJ/b/iteration to deliver a throughput of 9Gb/s at 10 decoding iterations.