A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise

This paper presents a fractional-N digital PLL achieving low in-band phase noise. The phase detection is carried out by a proposed 10-bit, 0.8 ps resolution TDC using a charge pump and a SAR-ADC, with low power and small area. The TDC enables wide loop bandwidth and low in-band phase noise of the PLL. A varactor-less and AE-less DCO using bridging capacitors is designed, achieving 7 kHz frequency resolution (or 2.6 aF unit variable capacitance). A counter-based architecture is used without requiring long conversion range of the TDC. A gating block gates out one pulse of DCO´s output at the reference frequency to accommodate the TDC to the PLL. The prototype chip is fabricated in 65 nm CMOS, occupying 0.38 mm2 active area and consuming 9.7 mW power. The measured in-band phase noise is -110 dBc/Hz at 600 kHz offset, at 3.625 GHz, with 5 MHz loop bandwidth.