A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters

A 12b 104MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented for a digitally-assisted wireless transmitter system for use in cellular applications. A power-on calibration technique is implemented to correct capacitor DAC mismatch and reduce capacitor size, thereby relaxing the current consumption of the input buffer and reference generator. The total capacitor size is reduced to 0.6pF from 3.6pF required for 12-bit matching. The ADC analog core area is 0.003mm². After calibration, this work achieves 88dB SFDR at 26MHz sampling rate and 76.2dB SFDR at 104MHz sampling rate. Measured DNL and INL are 0.5LSBs and 1. 1LSBs respectively. The ADC achieves both high speed and low power by combining several techniques: digital calibration, redundancy, asynchronous bit-cycling, monotonic switching, 25% duty-cycle sampling period, 3dB input gain, and a fully dynamic comparator The power consumption from 1.2V/1.1V supplies is 0.88mW for a single ADC core and 6.1-mW for the entire I/Q ADC, including the reference generator and input buffers. The ADC is fabricated in 28nm CMOS.